Nov 2023 - Dec 2023
Cache Simulator
Python simulator for analyzing direct-mapped and set-associative cache behavior.
Cache Simulator models cache memory behavior using configurable command-line inputs, direct-mapped and set-associative designs, tag matching, LRU replacement, and memory address parsing.
Conceptual Visual
Memory Hierarchy
CPU
Cache
Main Memory
Tag / Index / Offset
Hit / Miss
Highlight
Direct-Mapped Cache
Highlight
Set-Associative Cache
Highlight
LRU Replacement
Highlight
CLI Configuration
Executive Summary
Cache Simulator models cache memory behavior using configurable command-line inputs, direct-mapped and set-associative designs, tag matching, LRU replacement, and memory address parsing.
Problem Statement
Cache behavior is easier to reason about when hits, misses, tags, sets, and replacement policies can be inspected directly.
What I Built
Configurable cache settings
Hit/miss tracking
Tag matching
LRU replacement
CLI execution
How It Works
A conceptual workflow showing how the project moves from input to processing and output.
Step 1
Memory Address
Step 2
Tag / Index / Offset Parsing
Step 3
Cache Lookup
Step 4
Hit / Miss Decision
Step 5
LRU Update
Architecture / System Design
A simplified system view of the major project components and how responsibilities connect.
Step 1
CLI Args
Step 2
Cache Config
Step 3
Address Parser
Step 4
Cache Engine
Step 5
Statistics Output
Technical Implementation
Cache Models
- Direct-mapped cache
- Set-associative cache
- Configurable cache parameters
Address Logic
- Tag extraction
- Index calculation
- Offset parsing
Replacement
- LRU behavior
- Hit/miss tracking
- State updates
Tools
- Python
- Ubuntu Linux
- CLI configuration
Visual Showcase
Conceptual preview panels for the project experience. These are intentional placeholders, not fake screenshots.
Cache Table Preview
Conceptual cache-state table with sets, tags, and valid entries.
Hit/Miss Flow
Visual path from address parsing to cache decision.
Address Breakdown Panel
Tag/index/offset split presented as a systems diagram.
CLI Output Preview
Terminal-style memory access trace.
Access Trace Preview
access 0x1A3F -> set=3 tag=0x68 -> HIT
access 0x2B41 -> set=1 tag=0xAD -> MISSChallenges & Solutions
Challenge
Cache mapping behavior can be difficult to inspect from theory alone.
Solution
Created traceable hit/miss decisions from configurable memory accesses.
Challenge
Set-associative caches need replacement policy behavior.
Solution
Implemented LRU tracking to update cache state across accesses.
Results / Impact
Demonstrates practical software engineering through modular structure, readable workflows, and clear technical documentation.
Shows ability to convert course and research concepts into working systems with real implementation constraints.