Jan 2025 - Mar 2025
MIPS CPU Simulator
Python-based instruction set simulator for fetch-decode-execute CPU workflows.
MIPS CPU Simulator is a modular Python system that models instruction-level execution for MIPS-like programs. It implements fetch, decode, execute, register updates, memory access, branch handling, and cycle-by-cycle execution tracing.
Conceptual Visual
CPU Pipeline Trace
Instruction Input
Fetch
Decode
Execute
Memory
Writeback
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Fetch-Decode-Execute
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Modular CPU Engine
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Register + Memory System
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Cycle-by-Cycle Trace
Executive Summary
MIPS CPU Simulator is a modular Python system that models instruction-level execution for MIPS-like programs. It implements fetch, decode, execute, register updates, memory access, branch handling, and cycle-by-cycle execution tracing.
Problem Statement
Understanding CPU execution requires visibility into how instructions move through the processor pipeline and affect registers, memory, and control flow. This simulator makes low-level execution transparent and easier to test.
What I Built
Instruction parsing
Register updates
Memory access
Branch handling
CLI execution traces
How It Works
A conceptual workflow showing how the project moves from input to processing and output.
Step 1
Assembly Instruction
Step 2
Parser
Step 3
Control Unit
Step 4
ALU / Memory
Step 5
Register Update
Step 6
Execution Trace
Architecture / System Design
A simplified system view of the major project components and how responsibilities connect.
Step 1
CLI Input
Step 2
CPU Engine
Step 3
Control Unit
Step 4
Register File
Step 5
Memory System
Step 6
Trace Output
Technical Implementation
CPU Engine
- Fetch/decode/execute flow
- Branch handling
- Cycle-by-cycle trace generation
Control Unit
- Instruction interpretation
- Control signal structure
- Execution path selection
State Systems
- Register file
- Memory model
- Write-back updates
Tools
- Python
- CLI execution
- Trace-oriented debugging
Visual Showcase
Conceptual preview panels for the project experience. These are intentional placeholders, not fake screenshots.
CPU Pipeline Diagram
Conceptual instruction path across fetch, decode, execute, memory, and writeback.
Register File Preview
Intentional table-style panel for register state changes.
Memory Table Preview
Conceptual memory-state panel for load and store operations.
Cycle Trace Terminal
Terminal-style preview of instruction execution across cycles.
Cycle Trace Preview
cycle 01: fetch addi $t0, $zero, 5
cycle 02: decode opcode=addi
cycle 03: execute ALU result=5
cycle 04: writeback $t0=5Challenges & Solutions
Challenge
CPU execution is hard to understand when register and memory changes are hidden.
Solution
Generated cycle-by-cycle traces that expose instruction flow and state updates.
Challenge
Assignment implementations can become fragmented across CPU responsibilities.
Solution
Refactored into a modular CPU engine, control unit, register file, and memory system.
Results / Impact
Demonstrates practical software engineering through modular structure, readable workflows, and clear technical documentation.
Shows ability to convert course and research concepts into working systems with real implementation constraints.